Fabrication of three dimensional (3D) memory devices (e.g., 3D NAND memory) involves patterning of stacks of dielectric layers, where one individual stack may include more than ten, twenty or even fifty layers. Patterning of such stacks on a semiconductor substrate is often performed by depositing a relatively thick hardmask layer over the top layer of the stack, patterning the hardmask to expose the underlying layer in a desired pattern, and etching the exposed underlying layer while not fully removing the hardmask.
The hardmask material should have an excellent etch selectivity versus the etched dielectric, it should have a good adhesion to the underlying dielectric layer and, importantly, it should not cause substantial substrate bowing due to stress. Two types of stresses contribute to deformation of the substrate—compressive stress and tensile stress. When the hardmask material is compressive (i.e., has compressive stress), the hardmask pushes onto the substrate and bows the substrate downward. When the hardmask material is tensile (i.e., has tensile stress), the hardmask pulls the substrate upward. Typically the absolute value of the substrate bowing increases with the increasing thickness of the hardmask. Therefore, in applications where thick hardmasks are needed, the stress of the hardmask materials should be particularly low in order to minimize the substrate bow. In some applications moderate stress may be desired to compensate for the existing stress of the stack.
In conventional processing carbon is often used as a hardmask material for patterning of the 3D memory stacks. However, thick carbon films can cause undesirably large stress-induced substrate bowing. New materials with lower stress and high etch selectivity are needed for hardmask applications.